blog
this has all led to a fairly large change in development environment, i now have the following in emacs
- eglot (LSP)
- company-mode (autocompletion)
- have left the terminal! i use the GUI
- a nice start-of-day function that sets the frames and tabs up how i like
as this is a makefile project, it needs a clang compile_commands.json for the clang utilities to work. this is done with bear which was in the debian repos. all that is done is either: call make through bear bear -- make -j or(if there are existing build remains) make compile_commands.json
it wasnt so good at the start as clang-format(which eglot-format-buffer uses) uses the wrong formatting style. this was fairly straightforward to configure though so not too bad
clang-tidy is a big beast, it can be fooled into breaking things by telling it to fix code enough times!(im still learning lots about modern C++!) but can be reigned in like other static analysers... i settled on the following checks configuration performance*,modernize*,-modernize-use-trailing-return-type,readability*,-readability-redundant-control-flow,-readability-identifier-length,-readability-magic-numbers,-modernize-redundant-void-arg,-readability-else-after-return,-modernize-use-equals-default,-modernize-pass-by-value which seem reasonable?
all of this because i want to be able to control some instruments!
there are loads of quality improvements though
- docs
- proper compiler error flags
- unit testing
docs are simple and are being worked on, when reasonable docs will move over to being an ongoing process
compiler error flags should have been done when the Makefiles were written and there is a big chance that enabling the normal -Wall -Werror -Wextra flags will cause some nontrivial rework
unit testing will be new, ive only done a little bit of CPP unit testing and that was in TESSY which is out of my price range
when the SDM3055-SC driver with scancard support is written it will implement a new scanningDMM interface
there is now also some minimal support for gitea actions
i may put some form of protection on the ethernet lamps, they dont have any right now
i put the design into aisler to get a RoM cost on the PCB and it is expensive at about £50 per PCB and MOQ of 3 which gives a total PCB cost of £100 per switchBox. this means it needs to be as close to perfect as possible as its very much a oneshot as theres probably about the same in components on the PCBA still, it should be fine...right?
the contact connectors were revisited and actually the chosen part was fine, the model was incorrect but the chosen part was fine and its BoM information is now populated
the PCB is almost done just needing:-
- ethernet
- silkscreen tidying
- routing final look
- DRC
- any additional silkscreen
then it will be on to software! its been a long time coming